package ygo

import (
	"fmt"
	)

func register(
	decodeRegister		chan	DERE,
	muxRegister		chan 	MURE,
	registerDmux		chan	REDM) {

	var (
		i int32
		register [32] int32
	)

	for i=0; i<32; i++ {
		register[i] = i
	}
	//register[0] = 2147483648
	//register[1] = 2147483648
	//register[0] = 5
	register[8] = 12
	register[4] = 0
	register[0] = 0

	for{
		dere :=<- decodeRegister
		fmt.Println("[REG] DERE <-- DECODE")

		switch dere.RF_COMMAND{
			case RRS_RRT_WRD:
				fmt.Println("[REG] REDM --> DMUX (cmd: RRS_RRT_WRD)")
				registerDmux <- REDM{BUS1: register[dere.RS], BUS2:register[dere.RT]}

				mure := <- muxRegister
				if mure.CANCELLED == false {
					register[dere.RD] = mure.WRITE
					fmt.Println("[REG] Resultado armazenado")
				}
				fmt.Println("[REG] Resultado:", register[dere.RD])
				
			case RRS_WRT:
				fmt.Println("[REG] REDM --> DMUX (cmd: RRS_WRT)")
				registerDmux <- REDM{BUS1: register[dere.RS], BUS2:0}

				mure := <- muxRegister
				
				if mure.CANCELLED == false {
					register[dere.RT] = mure.WRITE
					fmt.Println("[REG] Resultado armazenado")
				}
				fmt.Println("[REG] Resultado:", register[dere.RT])

			case RRS_RRT:
				fmt.Println("[REG] REDM --> DMUX (cmd: RRS_RRT)")
				registerDmux <- REDM{BUS1: register[dere.RS], BUS2:register[dere.RT]}
		}
	}


}
